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[MiddleWare] fftipcore

Description: 该程序是vhdl语言编写的fft变换的ip核代码，程序中共包含了36个.vhd文件-that the procedure was prepared by the vhdl language fft transform ip nuclear code CPC procedures contained 36. vhd documents
Platform: | Size: 29696 | Author: 袁汇 | Hits:

[VHDL-FPGA-Verilog] cpu86model

Description: 关于8086的软核fpga代码，可以直接再fpag的开发板上调试，好用而且是免费的-on the 8086 soft-core fpga code can then direct the development fpag board debugging, handy and free
Platform: | Size: 270336 | Author: 赵春生 | Hits:

[VHDL-FPGA-Verilog] 8051core_vhdl

Description: 8051的内核(vhdl) This is version 1.1. of the MC8051 IP core. 在FPGA上运行.供有精力的人研究.-8051 kernel (vhdl) This is version 1.1. Of the M C8051 IP core. FPGA operation. have the energy for the study.
Platform: | Size: 212992 | Author: efly | Hits:

[Compress-Decompress algrithms] fft

Description: VHDL语言编写的fft变换的ip核代码 对算法感兴趣的可以-VHDL language fft transform algorithm ip core code can be interested in
Platform: | Size: 459776 | Author: liujl | Hits:

[VHDL-FPGA-Verilog] smj_etester

Description: 脉宽测试仪FPGA芯片的VHDL核心程序-Pulse width Tester FPGA chip VHDL core procedures
Platform: | Size: 1024 | Author: 孙明杰 | Hits:

[MPI] small

Description: 硬件描述语言VHDL的最小内核nios设计,满足了内核的基本需要。-VHDL hardware description language of the smallest core Nios design, to meet the basic needs of the core.
Platform: | Size: 2048 | Author: 李梧桐 | Hits:

[Other Embeded program] DW8051_2

Description: DW8051 高速8051 IP Core, 本人測試過完全100％ 正常.-DW8051 High-Speed 8051 IP Core, I tested 100 percent completely normal.
Platform: | Size: 67584 | Author: eddche | Hits:

[VHDL-FPGA-Verilog] ip_fft128

Description: 128点fft的IP核vhdl源代码，另有其控制代码。-128 point fft s IP core VHDL source code, while its control code.
Platform: | Size: 7168 | Author: 戈立军 | Hits:

[Software Engineering] 567

Description: The paper presents the CORDIC Algorithm, which has been implemented as an virtual component (IP core) in a VHDL simulation environment. The core is packaged as a soft (VHDL) macro and it implements all transcenden-tal functions. Analysis of the accuracy of the algorithms implemented shows that the CORDIC functions are equivalent to the accuracy of a Pentium coprocessor.
Platform: | Size: 117760 | Author: 赵平 | Hits:

[ARM-PowerPC-ColdFire-MIPS] uP8051VHDL

Description: 一个电驴上下的51的CORE，可以综合，自己没跳过-EDonkey up and down a 51 of CORE, can be integrated, their not skip
Platform: | Size: 316416 | Author: youjia | Hits:

[VHDL-FPGA-Verilog] fftinterface

Description: 电赛一等奖作品：音频信号分析仪的FPGA源码，VHDL编写，Quartus7.1综合，ModelSim6.2g se仿真，应用了opencores.org上的开源FFT IP核，加入了8051总线接口和ram-Xinhua Cup first prize works: audio signal analyzer FPGA source, VHDL prepared, Quartus7.1 integrated, ModelSim6.2g se simulation, application of open source opencores.org on FFT IP core, joined the 8051 bus interface and ram
Platform: | Size: 4933632 | Author: 李星 | Hits:

[VHDL-FPGA-Verilog] pci_express_crc

Description: PCI express CRC rtl core for Fpga/asic Designer
Platform: | Size: 202752 | Author: 李晓媛 | Hits:

[VHDL-FPGA-Verilog] 8051-vhdl-code

Description:
Platform: | Size: 98304 | Author: 周华茂 | Hits:

[VHDL-FPGA-Verilog] 6-portRegisterFile

Description: 6端口寄存器IP内核VHDL源代码，所需的开发环境是QUARTUS II 6.0。-6-port register IP core VHDL source code, required for the development environment is QUARTUS II 6.0.
Platform: | Size: 28672 | Author: 周华茂 | Hits:

[VHDL-FPGA-Verilog] BIST_Circuits

Description: BIST 电路IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-BIST circuits IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
Platform: | Size: 5120 | Author: 周华茂 | Hits:

[VHDL-FPGA-Verilog] SoC_WishboneSystem

Description: SoC-Wishbone System IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-SoC-Wishbone System IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
Platform: | Size: 91136 | Author: 周华茂 | Hits:

[VHDL-FPGA-Verilog] core_arm.tar

Description: ARM7系统IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-ARM7 System IP Core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
Platform: | Size: 666624 | Author: 周华茂 | Hits:

[VHDL-FPGA-Verilog] keyboardcontroller.tar

Description: 键盘控制电路IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-Keyboard control circuit IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
Platform: | Size: 5120 | Author: 周华茂 | Hits:

[VHDL-FPGA-Verilog] sdram_ctrl.tar

Description: SDRAM控制IP核的VHDL语言源代码，需要的开发环境是QUARTUS II 6.0。-SDRAM control IP core VHDL language source code, the need for the development environment is QUARTUS II 6.0.
Platform: | Size: 88064 | Author: 周华茂 | Hits:

[VHDL-FPGA-Verilog] cfft

Description: CFFT是一个数据宽度和点数都可配置的基4 FFT core,用VHDL实现-CFFT is a data width and the base points can be configured 4 FFT core, using VHDL realize
Platform: | Size: 168960 | Author: | Hits:
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